Nanoscale Static Random-Access-Memory Design Using Strained Underlap Ultra Thin Silicon on Insulator MOSFET for Improved Performance

Recent Samsung's announcement of mass production of fully depleted ultra thin silicon on insulator (UTSOI) at 28 nm process node develops fresh interest among the researchers for developing next process node of UTSOI. Below 28 nm feature size, USTOI come across various design challenges like high leakage current, lower driving capability and lesser gate controllability over channel. In this work, UTSOI with gate underlap and strained silicon channel (SUL) has been used to lower the leakage current and enhance the ON current (I _ON) respectively. The high-k spacer is also incorporated in SUL to address gate controllability problem. We have shown the impact of different high-k spacer on I _ON, OFF current (I _OFF), total gate capacitance (C _GG) and drain induced barrier lowering (DIBL). For the first time, we have explored the application of SUL device in circuit such as static RAM (SRAM). The proposed device also addresses the conflicting requirements of read and write operations. The results have shown that the SUL based SRAM achieves better read stability without degrading the write-ability of the SRAM cell. The proposed SRAM has also achieved 61% lower leakage power consumption than conventional SRAM due to the significant reduction of gate leakage current, OFF state current and subthreshold leakage current.