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A Model to Improve Analysis of CNTFET Logic Gates in Verilog-A-Part I: Static Analysis

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In this paper we have implemented a simple DC model for CNTFETs already proposed by us in order to carry out static analysis of basic digital circuits, with a significant improvement compared to Wong model. In particular we have obtained a lighter ensuring compile and shorter execution time, without losing in accuracy.
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Keywords: CNTFETs modelling; digital applications; noise margin; sub threshold currents

Document Type: Research Article

Publication date: August 1, 2015

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  • Current Nanoscience publishes authoritative reviews and original research reports, written by experts in the field on all the most recent advances in nanoscience and nanotechnology. All aspects of the field are represented including nano- structures, synthesis, properties, assembly and devices. Applications of nanoscience in biotechnology, medicine, pharmaceuticals, physics, material science and electronics are also covered. The journal is essential to all involved in nanoscience and its applied areas.
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