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Designing High Speed Sequential Circuits by Quantum-Dot Cellular Automata: Memory Cell and Counter Study

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According to the high rate of dimensions shrinkage in conventional CMOS circuits, serious challenges threat this technology. Quantum-dot cellular automata is a well-known and possible solution for replacement of CMOS technology. Designing robust and efficient QCA-based sequential circuits is a significant subject which needs well-organized structures for latches. Therefore, in this paper we try to present two novel and innovative designs for these kinds of circuits. Firstly we propose an efficient architecture for random access memory cell with set and reset ability which is based on the D-latch and secondly we present a high speed JK-latch which is appropriate for implementation of different QCA sequential circuits and we implement a 2-bit synchronous counter using this latch. Both designs have improvements in terms of complexity and computation speed versus state-of-the-art. Simulation results achieved from QCADesigner tool authenticate the accuracy and usefulness of proposed architectures.
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Keywords: D LATCH; JK LATCH; NANOELECTRONICS; QUANTUM-DOT CELLULAR AUTOMATA; RAM CELL; SET AND RESET ABILITY; SYNCHRONOUS 2-BIT COUNTER

Document Type: Research Article

Publication date: April 1, 2015

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  • QUANTUM MATTER is a peer-reviewed interdisciplinary journal consolidating research activities in all theoretical, experimental and technological aspects dealing with fundamental structure of matter from cosmology to materials science.
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