Parametric Study of Low-k Layer Stress for a Flip-Chip Chip Size Package Using a Copper Pillar Bump

In this work, we investigated the failure mechanism of a flip-chip chip size package with a low-k layer using a copper pillar bump by experimental and numerical analysis. We observed damage on the Cu pillar bump process due to excessive induced stress after the chip attach reflow; a feature known as white bump. The maximum tensile stress was concentrated on the Al pad and the interface between the low-k layer and Al pad, which were the possible sites for crack initiation and delamination. In order to prevent the low-k failure, the effects of five parameters on the low-k layer stress were systematically investigated, which were the under bump metallization (UBM) diameter, die thickness, die size, coefficient of temperature expansion (CTE) of the substrate core, and diameter of the solder resist opening. Numerical simulation results indicated that larger UBM, thinner die and lower CTE core materials were beneficial for reducing the stress on the low-k layer. Application of the optimized parameters reduced the low-k layer stress by 50%.