A Fast Calibration Current Steering DAC with Bypass Window Under 55 nm CMOS Process
Attaining fast calibration, energy-efficiency and less chip area is important for design of high-speed and high-accuracy digital-to-analog converters in nanometer process, especially in mobile communication system or electronic systems which utilize batteries to supply the power. This work presents a fast calibration technique with bypass window, which shrink chip area and optimizes calibration sequence to skip several conversion steps when the signal is within the predefined window. A behavioral model of a 14-bit segmented digital-to-analog converters was implemented, and the chip area of the most significant bits current source arrays shrinks by 8 times. According to the digital calibration, the differential non-linearity and integral non-linearity are both smaller than 0.5LSB. Due to the introduction of bypass window technique, the calibration time and power consumption are reduced by up to 13%.
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Document Type: Short Communication
Publication date: April 1, 2015
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- Nanoscience and Nanotechnology Letters (NNL) is a multidisciplinary peer-reviewed journal consolidating nanoscale research activities in all disciplines of science, engineering and medicine into a single and unique reference source. NNL provides the means for scientists, engineers, medical experts and technocrats to publish original short research articles as communications/letters of important new scientific and technological findings, encompassing the fundamental and applied research in all disciplines of the physical sciences, engineering and medicine.
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