An Ultra-Low Power Successive-Approximation-Register Analog-to-Digital Converter with Input-Referred Amplifier-Skipping Window Technique in 55 nm Low-Leakage Process
This paper presents an ultra-low power successive-approximation-register (SAR) analog-to-digital converter (ADC) for biomedical applications. To reduce power consumption, an input-referred amplifier-skipping window (IRAS Window) technique is employed. The preamplifier in front of the comparator is disabled for power saving when the input signal is out of the predefined window size. Stack forcing and multi-V t design approaches are used to reduce the leakage current. With the 55 nm low-leakage process and a 0.6 V power supply, the ADC achieves a SNDR of 73.2 dB (11.86 bits ENOB) and a SFDR of 83.9 dB at 10 kS/s sampling rate. Total power consumption is 284 nW, yielding a figure of merit of 7.6 fJ/conversion-step.
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Document Type: Short Communication
Publication date: September 1, 2014
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