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Design and Optimization of a Milli-Meter Wave Amplifier Using Nano-Scale CMOS Devices

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This letter reviews some fundamental trade-offs in RF amplifier design as well as optimization from devices to circuit design using nano-scale CMOS process, that reduces the impact of manufacturing variations on integrated wideband low noise amplifiers (LNA). The design considerations include the unity-gain frequency, high frequency noise, power consumption and linearity of active devices in addition to accurate physic models for passive components such as RF and transmission lines. All these considerations are traded off among a system designs aspect. For an example in a commercial 65 nm CMOS technology design, by optimizing the unity width of the transistors and the transmission lines, a three-stage LNA achieves a peak gain of 22.3 dB at 60 GHz with a Noise Figure of 5.17 dB. Each stage consumes 5.2 mA from a supply voltage of 1.5 V. By using Monte Carlo simulation, the LNA with optimized transistor and interconnects has a higher gain and lower Noise Figure. The circuit is able to work robustly against process variations by optimizing the transistors and the transmission lines.
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Keywords: CMOS; LNA; NANO-SCALE; OPTIMIZATION; PROCESS VARIATION

Document Type: Short Communication

Publication date: September 1, 2014

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  • Nanoscience and Nanotechnology Letters (NNL) is a multidisciplinary peer-reviewed journal consolidating nanoscale research activities in all disciplines of science, engineering and medicine into a single and unique reference source. NNL provides the means for scientists, engineers, medical experts and technocrats to publish original short research articles as communications/letters of important new scientific and technological findings, encompassing the fundamental and applied research in all disciplines of the physical sciences, engineering and medicine.
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