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Considerations and Optimization of Measurement Accuracy of Capacitance in Nano-Scale CMOS Technology

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In this letter, various factors which affect the measurement accuracy of capacitance in nano-scale CMOS technology are discussed. A charge based capacitance measurement (CBCM) test structure with optimized parameters is presented. It has a higher measurement accuracy and narrower range of error, which are demonstrated by the Monte Carlo simulation. The circuit is designed and simulated in a standard 65 nm CMOS technology and is able to work robustly against process variations with sub-femto-farad resolution.
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Keywords: CAPACITANCE MEASUREMENT; CBCM; CMOS; NANO-SCALE; OPTIMIZATION; PROCESS VARIATION

Document Type: Short Communication

Publication date: September 1, 2012

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  • Nanoscience and Nanotechnology Letters (NNL) is a multidisciplinary peer-reviewed journal consolidating nanoscale research activities in all disciplines of science, engineering and medicine into a single and unique reference source. NNL provides the means for scientists, engineers, medical experts and technocrats to publish original short research articles as communications/letters of important new scientific and technological findings, encompassing the fundamental and applied research in all disciplines of the physical sciences, engineering and medicine.
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