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Design of Nano-Scale Noise Tolerant CMOS Logic Circuits Based on Probabilistic Markov Random Field Approach

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Scaling down of the CMOS technology into the sub-50 nm regime has made the nature of digital computation from deterministic to probabilistic. Noise tolerance is becoming equally important to power, speed and area in nano-scale VLSI computational systems. In this letter, a probabilistic-based Markov Random Field (MRF) design methodology is combined with the Differential Cascode Voltage Switch (DCVS) circuit topology to design a novel nano-scale CMOS XOR-NXOR circuit. The proposed design is implemented in 40 nm CMOS technology and presents superior noise immunity over traditional designs with low power consumption.
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Document Type: Short Communication

Publication date: September 1, 2012

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  • Nanoscience and Nanotechnology Letters (NNL) is a multidisciplinary peer-reviewed journal consolidating nanoscale research activities in all disciplines of science, engineering and medicine into a single and unique reference source. NNL provides the means for scientists, engineers, medical experts and technocrats to publish original short research articles as communications/letters of important new scientific and technological findings, encompassing the fundamental and applied research in all disciplines of the physical sciences, engineering and medicine.
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