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Open Access A Multiple Input Floating Gate Based Arithmetic Logic Unit with a Feedback Loop for Digital Calibration

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We present the design of a 32-bit ALU using multiple input floating gate MOSFETs. Using the reconfigurable surface potential applied on the device, Boolean logic operations such as addition, subtraction and sequence comparison can be performed in the feedforward path. We have built a feedback loop to guide the ALU to implement the error detection. Using TSMC 180 nm CMOS technology, the post layout simulation shows that the power dissipation of the proposed ALU varies from 0.0394 W to 0.207 W when the frequency varies from 0.5 GHz to 2 GHz. The computation delay in this design is less than 10 ns under 10 fF load. Compared to the same ALU built in static logic, the proposed one using multiple input floating gate logic has the advantages of energy saving and large tolerance in fan-out. Besides, introduced feedback loop does not bring large overhead to the ALU.

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Keywords: ARITHMETIC LOGIC; ERROR DETECTION; MULTIPLE INPUT FLOATING GATE (MIFG) MOSFET; NEURON-LIKE CELL; UNIT (ALU)

Document Type: Miscellaneous

Publication date: December 1, 2018

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  • The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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