Low Power SR-Latch Based Flip-Flop Design Using 21 Transistors

A low voltage and low power SR-latch based flip-flop design is proposed. It is adapted from a classic text-book-style all-NAND based flip-flop design and achieves circuit simplification by eliminating redundant logic. The optimization measure leads to a new design featuring better timing and power performance. The area and the power-delay-product of the proposed design also outperform those of the widely used transmission gate based flip-flop design significantly. The proposed design is further extended to a 6-bit Johnson counter using the TSMC 0.18 μm CMOS technology. When operating in the nominal condition, i.e., (0.5 V/1 MHz), the design has a measured power consumption of 21.57 nW. For the target 1 MHz working frequency, the required V_DD can be even reduced to 0.402 V and the power consumption is less than 10 nW.