Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions

Many techniques are reported in the literature for controlling power and temperature on a chip. This paper presents a technique that uses optimal supply and body-bias voltage assignment to establish the same. The technique is guided by novel analytical models proposed in this paper that yield accurate estimations of delay and power for multi-V _t designs in the presence of process-strength variations and temperature. These models incorporate base-line components of gate delay, interconnect delay, leakage power and dynamic power per V _t -class, which makes them accurate and scalable across designs. Further, to the best of our knowledge, the model proposed in this paper is the first reported in the literature that considers leakage through body-bias pin. This has resulted in high accuracy in leakage power estimation. Estimation of timing and power using the proposed model on a post-layout ARM^® processor block implemented using mixed-V _t cells (SVT and LVT) running at 1.25 GHz with TI^® 28 nm technology showed 3% RMS Error when compared with those reported using detailed timing and power analysis tool. With the use of these models along with a standard optimizer, it is shown that the optimized supply and body-bias voltage assignment for ARM^® processor block provides significant upto 39% (30%) run-time power reduction in the presence (absence) of on-chip temperature sensors when compared with ASV (a static process-strength aware adaptive supply voltage) conditions. Employing the proposed scheme on 3D Chip Multi-processor (CMP) designs at worst-case operating conditions (on-line system testing) show >35% power reduction and >8 °C peak temperature reduction over and above what is achieved by employing thermal and power management techniques reported in the literature.