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An Analytical Approach for Drain Current Modelling of a Symmetric Double Gate Junctionless Transistor

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In this paper a fully analytical approach for drain current modelling of a symmetric double gate junctionless transistor is presented. In this approach the channel is divided into a number of elementary segments where length of each segment is equal to the diameter of a silicon atom. Each of the segments may consists of either a depletion region or a neutral semiconductor region or both. When the gate voltage is between threshold voltage and flatband voltage, a segment is considered as a parallel combination of three resistances-one non-depleted layer resistance and other two are depleted layer resistances. In the subthreshold region the equivalent resistance reduces to a single depletion layer resistance and in the flatband region it reduces to a single non-depletion layer resistance. The equivalent resistance and potential difference for each segment is determined and hence using ohms law, current through each segment is determined. The current through one segment is nothing but the total drain current flowing through the channel. The model is validated by comparing it with the TCAD simulation results.
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Keywords: ANALYTICAL; DOUBLE GATE; DRAIN CURRENT; JLT; SYMMETRIC

Document Type: Research Article

Publication date: September 1, 2018

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  • Journal of Nanoelectronics and Optoelectronics (JNO) is an international and cross-disciplinary peer reviewed journal to consolidate emerging experimental and theoretical research activities in the areas of nanoscale electronic and optoelectronic materials and devices into a single and unique reference source. JNO aims to facilitate the dissemination of interdisciplinary research results in the inter-related and converging fields of nanoelectronics and optoelectronics.
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