Parasitic Capacitance and Resistance Model Development and Optimization of Raised Source/Drain SOI FinFET Structure for Analog Circuit Applications

Nowadays FinFET based structure has replaced the conventional MOS based structure almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets and smartphones at lower technology node. The scaling of the FinFET structure is continuously ongoing and performance of FinFETs in the integrated circuits suffers from the increased parasitic capacitance and resistance problems at lower performance nodes. The conventional capacitance and resistance model cannot be applied directly to the FinFET transistor in sub 20 nm technology node due to its three-dimensional non-planar geometry. In this paper, analytical capacitance and resistance models are developed for three-dimensional Raised source/drain (RSD) SOI FinFET structure and validity of these models are verified by three-dimensional (3-D) field solver Synopsys Raphael software. The developed parasitic capacitance and resistance models can be directly used in analog or nanoelectronic circuit applications for evaluating the accurate simulation results.