Thermo-Mechanical Stress Induced Electromigration in Cu and CNT Based TSVs Surrounding Various Dielectric Layers

Three-dimensional integrated circuit (3D IC) allows the assembly of disparate and multiple heterogeneous dies in a single chip. In a 3D IC, the through silicon vias (TSVs) are used to connect the vertically stacked dies. Due to very high integration, the TSV based 3D IC produces high temperature and exhibits significant mismatch in thermal expansion between the fillers in TSVs and surrounding materials. This will lead to thermo-mechanical stress resulting in electromigration and causing device/component failures. In this paper, finite-element analysis (FEA) is used to analyze the equivalent stress and resultant deformation due to atomic migration in TSVs. The copper (Cu) and carbon nanotubes (CNTs) based TSVs are analyzed for the comparison. Additionally, three different dielectric layers around TSVs, such as silicon dioxide, silicon nitride and benzocyclobuten (BCB) are used for the performance analysis. The comparison results show that CNT based TSVs have induced approximately 10⁵ times less stress compared to Cu based TSVs. It is also found that there is a little variation in the equivalent stress with SiO₂, Si₃N₄, and BCB dielectric layers. The CNT based TSVs exhibit significant reduction in equivalent stress and deformation with all the three combinations of dielectric layers over Cu based TSVs. Moreover, it is observed that mean time to failure (MTTF) is found in the order 10¹⁵ and 10⁹ hours in CNT and Cu TSVs, respectively. Due to more equivalent stress, deformation in the structure and much less MTTF compared to CNT TSV, Cu based TSV fails earlier for all the dielectric layers.