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Gate Tunneling Current Model of Scaled Strained Si n-MOSFET with Drain Induced Barrier Lowering Effects

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For scaled strained Si n-MOSFET devices, normal operation of devices is seriously affected due to static gate tunneling leakage currents with ultra-thin gate oxide of NMOSFET. To illustrate the impacts of gate leakage current on strained Si devices with Drain Induced Barrier Lowering (DIBL) effects, a theoretical model of gate tunneling currents following the analyses of quasi-two-dimension surface potential is presented in this paper. The devices performances were studied quantitatively using ISE simulator including different gate voltage and gate oxide thickness. The experiments show that simulation results well agree with theoretical analysis, and the theory and experimental data will contribute to VLSI design.
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Document Type: Research Article

Publication date: July 1, 2017

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  • Journal of Nanoelectronics and Optoelectronics (JNO) is an international and cross-disciplinary peer reviewed journal to consolidate emerging experimental and theoretical research activities in the areas of nanoscale electronic and optoelectronic materials and devices into a single and unique reference source. JNO aims to facilitate the dissemination of interdisciplinary research results in the inter-related and converging fields of nanoelectronics and optoelectronics.
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