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Design and Implement 1 Kb Array Employing Low-Power Low-Voltage 3T Gain-Cell Memory at 45 nm Scheme

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Logic compatible gain cell (GC)-embedded Dynamic Random Access Memory (eDRAM) arrays are considered as a replacement of Static RAM owing to their non-ratioed operation, small size, diminutive static leakage, and two-port functionality. However, to ease refresh rate and to reduce access times, conventional GC-eDRAM utilizes boosted control signals in order to write the cell through full voltage levels. With these boosted levels an additional power supply or on-chip charge pumps, as well as non-trivial level shifting and high voltage levels toleration are essential. In this work, we present logic compatible 3T GC-eDRAM that operates through a single voltage supply and offers enhanced write capability as well improved data retention to the conservative GC structures. At single supply of 700 mV and 27 °C temperature, proposed bit cell showing 4.58 ns data retention, 82.43 pA leakage of current and 128.2 pW leakage of power. The proposed circuit is established with a 1-Kb memory assortment targeted at low-power, energy-efficient applications that were designed on 45 nano meter node via CMOS technology. In the same technology node, proposed topology endows a bit cell area diminution of 48%, as compared to redrawn 6T (Six transistors) SRAM and diminution 72% of overall array area.
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Document Type: Research Article

Publication date: July 1, 2017

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  • Journal of Nanoelectronics and Optoelectronics (JNO) is an international and cross-disciplinary peer reviewed journal to consolidate emerging experimental and theoretical research activities in the areas of nanoscale electronic and optoelectronic materials and devices into a single and unique reference source. JNO aims to facilitate the dissemination of interdisciplinary research results in the inter-related and converging fields of nanoelectronics and optoelectronics.
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