Innovative Ground-Plane (GP) Architectures for Thin Body and Thin Buried Oxide (UTBB) Silicon-On-Insulator MOSFETs
In this work, we first investigate the effects of substrate depletion in ultra-thin body with thick buried oxide (UTB) and ultra-thin body with thin buried oxide (UTBB) for 25 nm gate length. Better short-channel effects (SCEs), particularly in improving Drain-Induced Barrier Lowering (DIBL) can be obtained with UTBB at negatively-biased substrate due to a ground plane-like behaviour. However, UTBB lost its advantages by demonstrating high DIBL when the substrate is in depletion. An innovative GP formation made of localized GP of p-type in the substrate underneath the channel (herein referred to as GP-B structure) shows good electrostatic control by effectively suppressing the substrate depletion effects as compared to other GP architectures. The work then continues for a UTBB device with L g = 10 nm with different gate configurations i.e., the single-gate (SG) and double-gate (DG) operation modes for different GP architectures. Further improvement on the electrostatic parameters can be achieved in DG configurations where the impact of different GP architectures are also more pronounced as compared to SG.
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Document Type: Research Article
Publication date: July 1, 2017
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- Journal of Nanoelectronics and Optoelectronics (JNO) is an international and cross-disciplinary peer reviewed journal to consolidate emerging experimental and theoretical research activities in the areas of nanoscale electronic and optoelectronic materials and devices into a single and unique reference source. JNO aims to facilitate the dissemination of interdisciplinary research results in the inter-related and converging fields of nanoelectronics and optoelectronics.
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