Different Ground Plane (GP) Architectures on 25 nm Single-Gate (SG) versus Double-Gate (DG) UTBB SOI MOSFETs from Analog and RF Perspectives
In this work, the effects of different ground plane (GP) architectures in Ultra-thin Body and Buried Oxide Silicon-on-Insulator MOSFETs (UTBB SOI MOSFETs) for 25 nm gate length (Lg = 25 nm) are investigated through 2D-numerical simulations. Comparisons on the RF figures of merit (FoM) are made not only for the different GP architectures, but also for single-gate (SG) and double-gate (DG) operation modes. In SG mode, the variations of intrinsic gain (Av ) performance are related to substrate effects, while no significant impact on the current gain cut-off frequency (ft ) performance are observed for different GP architectures. DG mode is superior in the digital domain but exhibits lower ft values than SG due to an increase of gate-to-gate parasitic capacitances (Cgg ). The results contribute to the identifications of GP architectures and gate configurations (SG or DG) that can be adopted in device design (depending on either digital or RF applications) to fulfil specific applications.
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Document Type: Research Article
Publication date: April 1, 2017
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- Journal of Nanoelectronics and Optoelectronics (JNO) is an international and cross-disciplinary peer reviewed journal to consolidate emerging experimental and theoretical research activities in the areas of nanoscale electronic and optoelectronic materials and devices into a single and unique reference source. JNO aims to facilitate the dissemination of interdisciplinary research results in the inter-related and converging fields of nanoelectronics and optoelectronics.
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