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Modeling of Grain Growth in the Polysilicon Channel Process of a Vertical NAND Flash Memory

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We present a phase-field model to simulate grain growth occurring in the polysilicon channel process, one of critical steps in fabricating a vertical NAND flash memory. The process is called solid-phase crystallization, that is, annealing following depositing an amorphous silicon film on a side wall of a channel hole. Prediction of grain structures and grain size is of great importance to process engineers because grain boundaries degrade the bit-line current flowing along the channel. A set of Allen-Cahn equations for a polycrystalline film were numerically solved by finite difference method using a parallel computing platform. Our model could successfully reproduce experimental trends on film thickness dependence of the final grain size.
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Document Type: Research Article

Publication date: April 1, 2017

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  • Journal of Nanoelectronics and Optoelectronics (JNO) is an international and cross-disciplinary peer reviewed journal to consolidate emerging experimental and theoretical research activities in the areas of nanoscale electronic and optoelectronic materials and devices into a single and unique reference source. JNO aims to facilitate the dissemination of interdisciplinary research results in the inter-related and converging fields of nanoelectronics and optoelectronics.
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