Low Power FinFET Based Operational Amplifier with Improved Gain at 45 nm Technology Regime

In communication and computing devices, the growing demand for high performance, battery-operated portable equipments have transferred the concentration from staid constraints (such as area, performance and reliability) to power consumption. In the present scenario there is a cardinal requirement to diminish power consumption for non-portable systems where power dissipation and leakage current are censorious concerns. In VLSI circuits and systems, power dissipation is still censorious because the leakage occurs when device is in inactive mode. To reduce the leakage power and leakage current in FinFET based operational amplifier, a new circuit technique called low power state technique is adduced in this paper. This approach reduces significant amount of power during active mode and also has an endowment of conserving the state in state retention mode 1. The op-amp electrical characteristics are obtained by employing Cadence Virtuoso tool for circuit simulation at 0.7 V input supply voltage. The simulated DC gain thus obtained is 65.4 dB in the active mode. The proposed FinFET based operational amplifier performance traits are studied and compared with the existing CMOS technology at 45 nm scale. Here, the effect of temperature variation on electrical characteristics of op-amp at 45 nm technology regime has been reconnoitered. Furthermore, by employing low power approach, the enhancement in slew rate has been significantly attained. The simulation results are given and concluded.