Silicon Nanowire Transistors for Implementing an Field Programmable Gate Array Architecture with Scan Chain

This study presents a Field Programmable Gate Array (FPGA) architecture that uses vertical, undoped silicon nanowire transistors with metal gates and utilizes scan chain approach to minimize wiring channels. The study starts with a brief description of the nanowire transistor, its SPICE model with RC parasitics, and continues with an in-depth analysis of circuit performance and power dissipation of CMOS nano-circuits used in this particular FPGA architecture. The device design cycle optimizes both the NMOS and PMOS nanowire transistors for minimal dynamic power dissipation. Each transistor is modeled using BSIMSOI; parasitic resistance and capacitance values are extracted for SPICE simulations. FPGA is composed of cluster blocks, each of which contains three 4-input Look-Up-Tables (4-LUT). Each 4-LUT can be programmed to implement either combinatorial logic or state machine. Scan chains are used to program a specific logic function for each 4-LUT, to define data-paths in a cluster and between clusters and to reduce wiring channels. Inter-cluster communication is established by an 8-bit wide data bus and 4 shared switch boxes placed at each corner of a cluster. Worst-case propagation delay for a 4-LUT is 20.8 ps from its clock input to its output; the worst-case inter-cluster wire delay is 4.8 ps between 2 diagonally adjacent clusters and 11.2 ps between 2 diagonal clusters placed at 4 cluster lengths away. Worst-case dynamic power dissipation of a 4-LUT is 2.8 W if there is no overlap between selector inputs to a 4-LUT and increases by 60 nW/ns of overlap at 10 GHz. FPGA layout contains silicon nanowire transistors placed in a fabric matrix where each NMOS (PMOS) transistor has 4 neighboring PMOS (NMOS) transistors and occupies approximately 0.16 cm².