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Sub-30 nm Gate Template Fabrication for Nanoimprint Lithography Using Spacer Patterning Technology

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In this study, we present a spacer patterning technology for sub-30 nm gate template which is used for nano-scale MOSFETs fabrication. A spacer patterning technology using a poly-silicon micro-feature and a chemical vapor deposition (CVD) SiO2 spacer has been developed, and the sub-30 nm structures by conventional dry etching and chemical mechanical polishing are demonstrated. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields a large-area template with critical dimension of minimum-sized features much smaller than that achieved by optical lithography.
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Document Type: Research Article

Publication date: February 1, 2011

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  • Journal for Nanoscience and Nanotechnology (JNN) is an international and multidisciplinary peer-reviewed journal with a wide-ranging coverage, consolidating research activities in all areas of nanoscience and nanotechnology into a single and unique reference source. JNN is the first cross-disciplinary journal to publish original full research articles, rapid communications of important new scientific and technological findings, timely state-of-the-art reviews with author's photo and short biography, and current research news encompassing the fundamental and applied research in all disciplines of science, engineering and medicine.
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