Area-Delay Efficient Logic Design in Quantum-Dot Cellular Automata Using Standard Wire Approach

Complementary Metal-Oxide Semiconductor (CMOS) lithography-based technology has emerged a promising innovation for the last four decades. The scaling-down trend of CMOS is exhibiting its physical fundamental limits; typically interconnections among components consume large area and increases complexity. Quantum-dot Cellular Automata (QCA) is a future alternative to the physical problems of CMOS. In this paper, efficient combinational logic design with minimum, area, complexity and delay have been proposed. Standard wire method has been used for the newly implemented circuits and removes the need to have multilayer and cross-overhead cells. This wire mechanism has advantages to remove the serious source of defects, which are probable to occur during the fabrication process. To make the use of standard wire approach, a new 3-input XOR gate using QCA has been proposed. In addition, the proposed 3-input XOR gate has been testified to design a new single layer efficient 1-bit Full-Adder circuit with explicit cells. The proposed adder design in contrast to its counterparts uses standard wire scheme and surpasses the best previous robust single layer wire crossing adder designs in terms of area, clock delay and circuit complexity. All the proposed designs are simulated using QCA Designer Ver. 2.0.3.