Design and Implementation of Run Time Digital System Using Field Programmable Gate Array–Improved Dynamic Partial Reconfiguration for Efficient Power Consumption

In VLSI era, the recent trend evolution of transducer systems develops the structure to provide more resolution and accuracy with minimum time, area and power consumption. Reconfiguration computing is essentially driven to develop the application flexibility at run time. By developing the technique of configuring array of programmable logic reprogramming of the technology will be exploit to achieve a reconfigurable systems. Field Programmable Gate Arrays (FPGAs) is designed to reconfigure the array system with interconnects and configuration of logic blocks. In order to manage and access the intellectual system in real time environment dynamic partial reconfiguration is implemented to provide minimum power consumption with less area and time. The performance analysis of the system is considered in terms of design flow completeness, configuration type and technology portability. It provide less reconfiguration time (˜4–5 ms) when compare to full reconfiguration (˜12 ms); also provides better performance with less power and area consumption. The results are obtained by using Cadence 45 nm CMOS technology with gpdk library functions.