Unified Compact Modeling of a Gate Tunneling Current Considering Image Force Induced Barrier Lowering for a Nanoscale N-MOSFET

The image force barrier lowering of gate oxide barrier is becoming an important aspect of metaloxide-semiconductor field-effect transistor (MOSFET) in nanoscale regime. Consequently, the modeling of gate tunneling current considering the image force barrier lowering effect is very important for the estimation of leakage power, especially for low power application. In this paper, compact model of gate tunneling current through a ultra thin gate oxide due to direct tunneling of charge carrier through channel region and source/drain overlap region is presented for a nanoscale MOSFET. The results obtained are in good agreement with the experimental data over the entire gate bias range, certifying the high accuracy of the proposed model. The simplicity of the proposed model is suitable enough to use it for the circuit simulator. The proposed model is capable of predicting the gate tunneling leakage current under all gate bias condition. It is investigated that barrier lowering due image force effect can not be neglected at nanoscale regime of MOS devices. The results provide a guideline to the severity of this effect at nano scale from the point of view of standby power consumption.