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Effect of Scaling Parameters of Laterally Double Diffused Metal Oxide Semiconductor Device on Drain Induced Barrier Lowering

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Drain induced barrier lowering (DIBL) occurs in Laterally Double Diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOSFET). In this paper, the effect of device channel length, gate length, oxide thickness and drain voltage on the DIBL has been presented. To study the effect of these parameters on DIBL, first an LDMOS device has been simulated using ATLAS SILVACO tool. The value of DIBL has been computed from transfer characteristics (I D vs. V GS) of the device. In one of the simulations drain voltage (V D) has been varied while keeping the other parameters constant and corresponding value for DIBL has been computed and plotted. The results show that DIBL reduces with increase in drain voltage. Similarly simulation studies have been conducted to examine the effect of channel length, gate length and oxide thickness on the DIBL of the device individually. These simulations have been carried out at two different drain voltages. The results have been plotted.
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Keywords: CHANNEL LENGTH; DIBL; GATE LENGTH; LDMOS; OXIDE THICKNESS; THRESHOLD VOLTAGE

Document Type: Research Article

Publication date: March 1, 2016

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  • JOURNAL OF COMPUTATIONAL INTELLIGENCE AND ELECTRONIC SYSTEMS publishes emerging research in the areas of the computational intelligence and electronic systems. JCIES publishes in all areas of computational intelligence design and applications: applications oriented developments, successful industrial implementations, design tools, technology reviews, computational intelligence education, and applied research, specific emphasis on power electronics, embedded systems, semiconductor devices, analogue circuits, digital electronics, microwave and millimeter-wave techniques, wireless and optical communications, sensors, instrumentation and medical electronics much more.
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