Efficient Run-Time System Support for High Performance Reliable Reconfigurable Systems

This paper presents and demonstrates efficient run-time system support for high performance reliable reconfigurable systems. Central to this is a novel inter-task communication mechanism which uses the FPGA's configuration port as an inter-task communication medium instead of conventional routing resources on the logic fabric. As a result, complex inter-task routing is completely eliminated, and tasks can be easily relocated across a chip in order to maximize performance and/or avoid emerging faults on-chip. This architecture allows for scalable, multi-task and multi-user applications on FPGAs, whereby hardware tasks behave like software tasks. The paper demonstrates this in the context of a real hardware implementation of a widely used data mining application, namely K-Nearest Neighbor Classifier (KNN) which achieves considerably high performance and reliability at a low speed overhead and footprint.