The Effect of Total Bits and Number of LFSRs on the Hardware Performance of Modified A5/1 Stream Ciphers

This paper is a study on the hardware implementation of the modified A5/1 stream cipher used for Global System for Mobile (GSM) communication. While software simulation is one of the possible methods used to test the security of the cryptographic algorithm, one must also consider the practicality of the algorithm’s design which ultimately is to be implemented into hardware, in line with the exponential increase in the need for high speed and high performance devices. Despite the numerous work reported on the design versus security trade-off of the A5/1, to the best of the author’s knowledge, none looked at the effect of the modified design parameters, specifically the total bits and number of linear feedback shift registers (LFSRs) on the power performance of the algorithm when translated into hardware. In this work, three modified designs, with varying number of LFSRs and total bits are looked at. An increase in the number of LFSRs is observed to result in the highest power consumption, while the combination of both increased total bits and LFSRs reduced this need for power slightly. It has been found that an increase in the number of total bits alone gave the best hardware performance overall.