A Digital Hearing Aid SoC Based on AHB-Lite Bus Matrix
This work presents the SoC (System-on-a-Chip) for the digital hearing aid of which market size is expected to increase hugely. The proposed SoC employs the powerful custom DSP (Digital Signal Processor), which has the scalable architecture for high throughput applications, and various peripheral IPs such as I2S, Timer, and GPIO. All blocks including SRAMs are connected with multi-layer bus matrix based on AMBA AHB-Lite which allows the short latency in transactions. The proposed chip has been fabricated with 65 nm CMOS process with 128 KB embedded SRAM.
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Document Type: Research Article
Affiliations: Department of Electrical and Information Engineering, Seoul National University of Science and Technology, Seoul, 01811, Republic of Korea
Publication date: November 1, 2016
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