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A 2-Stage Low Noise Amplifier in 90 nm CMOS for 2.4 GHz Applications

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In this paper, a 2-stage low noise amplifier (LNA) is implemented in a 90 nm CMOS technology for 2.4 GHz applications. The measurement results show a noise figure of 3.2 dB with a gain 19.9 dB. The circuit consumes 6 mA from a 1.2 V supply, and has 7.2 mW power consumption. The core size is 1.1 mm×0.95 mm and the chip size including pads is 1.34 mm×1 mm.
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Keywords: 2.4 GHz; CMOS; LNA

Document Type: Research Article

Affiliations: Department of Electronics Engineering, Chungnam National University, Korea

Publication date: November 1, 2016

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  • ADVANCED SCIENCE LETTERS is an international peer-reviewed journal with a very wide-ranging coverage, consolidates research activities in all areas of (1) Physical Sciences, (2) Biological Sciences, (3) Mathematical Sciences, (4) Engineering, (5) Computer and Information Sciences, and (6) Geosciences to publish original short communications, full research papers and timely brief (mini) reviews with authors photo and biography encompassing the basic and applied research and current developments in educational aspects of these scientific areas.
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