A Very Fast Modular Digital CMOS Comparator

In this paper we present the design of a fast digital magnitude comparator. Our design improves the speed of operation of the circuit by making use of low fan-in and fan-out gates. Independent of the comparator bit width, the maximum fan-in and fan-out of any gate of our comparator is two and three respectively. Since our comparator design is recursive in nature, so large bit width comparators can be easily and systematically developed from small bit width comparators. This feature makes our design highly suitable for VLSI applications. When our modular comparator was designed and simulated for 64 bits, in HSPICE using 45 nm BSIM4 model card for bulk CMOS, it showed an average power consumption of 3.76 mW and an average delay of 0.134 ns at 1 GHz.