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Publisher: Elsevier

Volume 74, Number 6, 2014

Editorial Board
pp. IFC-IFC(1)

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Introduction to JPDC special issue on computing with future nanotechnology
pp. 2439-2440(2)
Authors: Moritz, C. A.; Khasanvis, S.; Narayanan, P.

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RRAM-based FPGA for ''Normally Off, Instantly On'' applications
pp. 2441-2451(11)
Authors: Turkyilmaz, O.; Onkaraiah, S.; Reyboz, M.; Clermidy, F.; ; Anghel, C.; Portal, J. M.; Bocquet, M.

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Spintronic Threshold Logic Array (STLA)-A compact, low leakage, non-volatile gate array architecture
pp. 2452-2460(9)
Authors: Nukala, N. S.; Kulkarni, N.; Vrudhula, S.

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Emitter-coupled spin-transistor logic
pp. 2461-2469(9)
Authors: Friedman, J. S.; Peters, J. A.; Memik, G.; Wessels, B. W.; Sahakian, A. V.

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Modeling and simulation of a nanoscale optical computing system
pp. 2470-2483(14)
Authors: Pang, J.; Lebeck, A. R.; Dwyer, C.

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Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells
pp. 2484-2496(13)
Authors: Zhao, W. S.; Portal, J. M.; Kang, W.; Moreau, M.; Zhang, Y.; Aziza, H.; Klein, J. O.; Wang, Z. H.; Querlioz, D.; Deleruyelle, D.

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Heterogeneous graphene-CMOS ternary content addressable memory
pp. 2497-2503(7)
Authors: Khasanvis, S.; Rahman, M.; Moritz, C. A.

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Parameter variation sensing and estimation in nanoscale fabrics
pp. 2504-2511(8)
Authors: Zhang, J.; Rahman, M.; Narayanan, P.; Khasanvis, S.; Andras Moritz, C.

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Critical transistors nexus based circuit-level aging assessment and prediction
pp. 2512-2520(9)
Authors: Cucu Laurenciu, N.; Cotofana, S. D.

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Enabling design and simulation of massive parallel nanoarchitectures
pp. 2530-2541(12)
Authors: Frache, S.; Chiabrando, D.; Graziano, M.; Vacca, M.; Boarino, L.; Zamboni, M.

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