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Publisher: Elsevier

Volume 70, Number 10, 2010

Editorial Board
pp. IFC-IFC(1)

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Transactional memory
pp. 993-1008(16)
Author: Grahn, H.

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Adaptive locks: Combining transactions and locks for efficient concurrency
pp. 1009-1023(15)
Authors: Usui, T.; Behrends, R.; Evans, J.; Smaragdakis, Y.

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Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems
pp. 1042-1052(11)
Authors: Ferri, C.; Wood, S.; Moreshet, T.; Iris Bahar, R.; Herlihy, M.

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Extensible transactional memory testbed
pp. 1053-1067(15)
Authors: Harmanci, D.; Gramoli, V.; Felber, P.; Fetzer, C.

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Implementation tradeoffs in the design of flexible transactional memory support
pp. 1068-1084(17)
Authors: Shriraman, A.; Dwarkadas, S.; Scott, M. L.

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Acknowledgment to special issue reviewers
pp. 1085-1085(1)
Author: Grahn, H.

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