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Investigation of the Effect of Grain for Vertically Stacked NAND Flash Memory with a Poly-GaAs Channel

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The cell characteristics of a vertically stacked NAND (V-NAND) flash memory with a poly-GaAs channel are investigated for the effect of grain using a three-dimensional simulation method, and they are compared to V-NAND with a poly-silicon channel. Under the same physical conditions, it is confirmed that the initial status of the V-NAND flash memory with a poly-GaAs channel shows a higher drain current and higher threshold voltage, which provides a better feasibility to improve the V-NAND flash memory. Due to the grain, V-NAND flash memory with a poly-GaAs channel shows more degradation in cell characteristics as the grain length decreases and the trap density in the grain boundary increases, compared to the V-NAND with a poly-silicon channel. Here, we explain that the higher energy band diagram in the poly-GaAs channel causes these results. The values of the trap density and grain length in the poly-GaAs channel are very important; the trap density should be maintained at a value less than 9e–13 cm–2eV–1 and the grain length should be maintained at a value more than 50 nm in order to obtain better cell characteristics compared to the V-NAND with a poly-Si channel.

Keywords: 3D NAND FLASH MEMORY; GAAS CHANNEL; GRAIN BOUNDARY; TCAD SIMULATION

Document Type: Short Communication

Publication date: May 1, 2017

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  • Nanoscience and Nanotechnology Letters (NNL) is a multidisciplinary peer-reviewed journal consolidating nanoscale research activities in all disciplines of science, engineering and medicine into a single and unique reference source. NNL provides the means for scientists, engineers, medical experts and technocrats to publish original short research articles as communications/letters of important new scientific and technological findings, encompassing the fundamental and applied research in all disciplines of the physical sciences, engineering and medicine.
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