A Low-Power Clock-Less Pulse Width Modulator Architecture for Smart Imaging
In this paper, we present a novel low-power image sensor architecture based on a clock-less serial read-out scheme. We show the operating principles of the architecture, and discuss the details of the implementation of the pixel, which is able to perform the conversion from the analog to the time domain of the light value individually. The implemented proof-of-concept device consists of 6 × 12 pixels and is intended to validate and characterize the new read-out scheme designed for low power applications. The pixel and the read-out scheme are particularly suitable for embedding energy harvesting circuits, even though this part is not included into the design. Thanks to the clock-less serial read-out with embedded PWM interface, the sensor delivers still images at a variable frame rate, up to a maximum of more than 60 Kfps at the highest illumination, showing a dynamic range of at least 72 dB. A typical value of power consumption of the entire array is estimated about 35 nW at 1.6 V of power supply, with a figure of merit of 0.32 pW/(pixel · frame).
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Document Type: Research Article
Publication date: March 1, 2018
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- The electronic systems that can operate with very low power are of great technological interest. The growing research activity in the field of low power electronics requires a forum for rapid dissemination of important results: Journal of Low Power Electronics (JOLPE) is that international forum which offers scientists and engineers timely, peer-reviewed research in this field.
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