Journal of Low Power Electronics

Scheduling Instructions for Enhanced Performance and Energy Efficiency on a Clustered Architecture with Applications in Big-Data Sensor Networks
pp. 1-8(8)
Authors: Zeng, Sishu; Tang, Haijing; Yang, Xu

Design of Peripheral Circuits for the Implementation of Memory Array Using Data-Aware (DA) SRAM Cell in 65 nm CMOS Technology for Low Power Consumption
pp. 9-20(12)
Authors: Singh, Ajay Kumar; Saadatzi, Mohammad-Sadegh; Venkataseshaiah, C.

Reducing Power and Cycle Requirement for Fast Fourier Transform of Electrocardiogram Signals Through Low Level Arithmetic Optimizations for Cardiac Implantable Devices
pp. 21-29(9)
Authors: Mostafa, Safwat; John, Eugene

A Novel Error Detection Strategy for a Low Power Low Noise All-Digital Phase-Locked Loop
pp. 30-34(5)
Author: Nanda, Umakanta

Design of a New Electrical Model of Integrated LC Filter in DC–DC Converter
pp. 35-44(10)
Authors: Bensaci, A.; Hamid, A.; Flitti, A.; Lebey, T.; Bley, V.; Medjaoui, F. Z.

A Sub-1 V 100 mA Wide Capacitive Load Based Flipped Voltage Follower Low-Dropout Regulator Using Transient-Assisted Embedded Driving Stage
pp. 45-55(11)
Authors: Wang, Dong; Tan, Xiao Liang; Chan, Pak Kwong

Selected Articles from the 6th International Workshop on CMOS Variability, Salvador, Bahia, Brazil, September 1–4, 2015
pp. 56-57(2)
Authors: Reis, Ricardo; Azemard, Nadine

Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices
pp. 58-63(6)
Authors: Kheirallah, Rida; Ducharme, Gilles; Azemard, Nadine

Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology
pp. 64-73(10)
Authors: Wei, Zhaopeng; Jacquemod, Gilles; Lorenzini, Philippe; Hameau, Frederic; de Foucauld, Emeric; Leduc, Yves

Minimum Operating Voltage Due to Intrinsic Noise in Subthreshold Digital Logic in Nanoscale CMOS
pp. 74-81(8)
Authors: Veirano, Francisco; Silveira, Fernando; Naviner, Lirida