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Characterization of Variation Aware Nanoscale Static Random Access Memory Designs

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Threshold voltage variation due to random dopant fluctuations poses a major challenge to the 6-transistor (6T) SRAM scaling, in nanoscaled technologies. In order to continue to enjoy the benefits of CMOS scaling, various SRAM bitcell topologies were proposed which introduce a tradeoff between performance, stability and cell density. In this paper, the 6T SRAM and the alternative SRAM bitcells are investigated on a commercial CMOS 65 nm design platform and are quantified based on read stability, write stability and the impact of Vth and Lgate variations on the cell yield. The read SNM of the 8T, and the 10T cells are about 50% higher than the 6T cell. The 10T I and 10T II cells use write assist techniques which boost their write SNMs by 22%. The 10T III SRAM cell has an inherent feedback loop which improves its write SNM by 29.21%. The 8T, 10T I and 10T II cells show a 60% improvement in their mean read SNM values and at least 13% reduction in the standard deviation values in the presence of process variations. These cells pass the yield criterion comfortably with a considerable margin. The results demonstrate the scalability of SRAM cells and indicate that with proper cell topology and read/write assist techniques the scaling window is still open for SRAM in the Nanoscale regime.
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Keywords: MEMORY; PROCESS VARIATIONS; RELIABILITY; STABILITY; STATIC NOISE MARGIN (SNM); STATIC RANDOM ACCESS MEMORY (SRAM); YIELD

Document Type: Research Article

Publication date: April 1, 2010

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