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Performance Analysis of Impact of Source/Drain Doping Gradients Well as Roll-Off Widths on Gate Induced Drain Leakage of Double Gate Metal Oxide Semiconductor Field Effect Transistor

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This paper investigates the importance of overlap/underlap design of channel in Double Gate (DG) MOSFETs to improve Short Channel Effects (SCEs) and Gate Induced Drain Leakage (GIDL). A systematic study of GIDL is a very important analysis in DGMOSFET. Gate underlap architecture is useful to reduce the GIDL and improve the SCEs in DGMOSFET structure. The results show that steeper Source/Drain (S/D) doping gradients along with wider S/D roll-off width will be required for the device. In order to enhance short channel immunity, the ratio of S/D roll-off width to lateral straggle should be high for a wide range of S/D doping gradients. This research provides innovative solution for realizing opportunity of very low power devices as well as circuits through underlap DGMOSFETs.
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Keywords: DGMOSFET; OVERLAP/UNDERLAP CHANNEL; SHORT CHANNEL EFFECTS (SCES) AND GATE-INDUCED-DRAIN-LEAKAGE (GIDL); SOURCE/DRAIN DOPING GRADIENTS (D); SOURCE/DRAIN ROLL-OFF WIDTHS (MS)

Document Type: Research Article

Publication date: November 1, 2018

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  • Journal of Nanoelectronics and Optoelectronics (JNO) is an international and cross-disciplinary peer reviewed journal to consolidate emerging experimental and theoretical research activities in the areas of nanoscale electronic and optoelectronic materials and devices into a single and unique reference source. JNO aims to facilitate the dissemination of interdisciplinary research results in the inter-related and converging fields of nanoelectronics and optoelectronics.
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