@article {Zhichao:2017:1555-130X:724,
title = "Gate Tunneling Current Model of Scaled Strained Si n-MOSFET with Drain Induced Barrier Lowering Effects",
journal = "Journal of Nanoelectronics and Optoelectronics",
parent_itemid = "infobike://asp/jno",
publishercode ="asp",
year = "2017",
volume = "12",
number = "7",
publication date ="2017-07-01T00:00:00",
pages = "724-730",
itemtype = "ARTICLE",
issn = "1555-130X",
eissn = "1555-1318",
url = "https://www.ingentaconnect.com/content/asp/jno/2017/00000012/00000007/art00016",
doi = "doi:10.1166/jno.2017.2100",
keyword = "GATE TUNNELING CURRENT MODEL, STRAINED SI, DIBL, QUASI-TWO-DIMENSION SURFACE POTENTIAL",
author = "Zhichao, Zhao and Tiefeng, Wu and Jing, Li and Quan, Wang and Wanglong, Han",
abstract = "For scaled strained Si n-MOSFET devices, normal operation of devices is seriously affected due to static gate tunneling leakage currents with ultra-thin gate oxide of NMOSFET. To illustrate the impacts of gate leakage current on strained Si devices with Drain Induced Barrier
Lowering (DIBL) effects, a theoretical model of gate tunneling currents following the analyses of quasi-two-dimension surface potential is presented in this paper. The devices performances were studied quantitatively using ISE simulator including different gate voltage and gate oxide thickness.
The experiments show that simulation results well agree with theoretical analysis, and the theory and experimental data will contribute to VLSI design.",
}