Comprehensive Stress Effect of Thin Coatings and Silicon–Carbon Lattice Mismatch on Nano-Scaled Transistors with Protruding Poly Gate
Enhancing the mobility in metal-oxide-semiconductor field-effect transistors (MOSFETs) with narrow channel widths is highly sensitive to the stress effects of Si channel when related advanced strain engineering is introduced and is compatible with semiconductor processes. In practice, layouts have significant effect on the device performance, especially for the protruding gate width on shallow trench isolation structures. The geometric parameter is investigated by systematically analysing an n-channel MOSFET composed of silicon–carbon (SiC) stressors embedded in the source and drain (S/D) regions and a tensile contact etch stop layer (CESL) using three-dimensional finite element simulation. Tensile CESL (1.1 GPa) and a SiC S/D stressor with a carbon mole fraction of 1.65% are loaded on the structure. The difference in the interactive percentages between the mechanical bending effect of the CESL from the top of the poly gate and the downward force of the CESL adjacent to the spacer sidewall of the gate occurs when the protruding gate width is increased. Results indicate that mobility was highly enhanced by approximately 72.5% at a width of approximately 0.2 μm. The mechanical bending effect becomes dominant when the gate width is more than 0.2 μm. Consequently, the mobility gain decays and consequently converges toward a constant.
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Document Type: Research Article
Affiliations: Department of Power Mechanical Engineering, National Tsing Hua University, No. 101, Section 2, Hsinchu, Taiwan 30013, R.O.C
Publication date: February 1, 2020
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