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Partial Contact Etching and Gate Lowering on Tunneling Field Effect Transistor for Performance and Power Enhancement
In this paper, it is shown that MOL capacitance reduction is one of the major performance boosting knobs for the tunneling field effect transistor (TFET) used for logic application. Low driving current is the weakness of TFET in terms of switching speed, however it can gain advantage
fully from reducing MOL capacitance owing to negligible impact of MOL resistance degradation. We have proposed partial contact etching and gate height lowering to reduce MOL capacitance. As a result, 7.3% of delay improvement and 9.0% of reduced energy consumption is achieved with optimized
MOL structure.
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Keywords: FinFET; Low-Power Logic Device; MOL Structure Optimization; Parasitic Capacitance Reduction; Partially Etched Contact; Tunneling Field Effect Transistor
Document Type: Research Article
Affiliations: Department of Electrical and Computer Engineering (ECE), Seoul National University, 1 Gwanak-ro, Gwanak-gu, Seoul 151-742, Republic of Korea
Publication date: 01 October 2019
- Journal for Nanoscience and Nanotechnology (JNN) is an international and multidisciplinary peer-reviewed journal with a wide-ranging coverage, consolidating research activities in all areas of nanoscience and nanotechnology into a single and unique reference source. JNN is the first cross-disciplinary journal to publish original full research articles, rapid communications of important new scientific and technological findings, timely state-of-the-art reviews with author's photo and short biography, and current research news encompassing the fundamental and applied research in all disciplines of science, engineering and medicine.
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