@article {Kim:2017:1533-4880:8338,
title = "Effects of Line-Edge Roughness on Extreme Ultraviolet Lithography CDs and Fin-Field-Effect-Transistor Performance for Below 10-nm Patterns",
journal = "Journal of Nanoscience and Nanotechnology",
parent_itemid = "infobike://asp/jnn",
publishercode ="asp",
year = "2017",
volume = "17",
number = "11",
publication date ="2017-11-01T00:00:00",
pages = "8338-8343",
itemtype = "ARTICLE",
issn = "1533-4880",
eissn = "1533-4899",
url = "https://www.ingentaconnect.com/content/asp/jnn/2017/00000017/00000011/art00091",
doi = "doi:10.1166/jnn.2017.15141",
keyword = "Line Edge Roughness, EUV, Lithography, FinFET, Lithography Simulation, LER",
author = "Kim, Sang-Kon",
abstract = "As the critical dimension (CD) of electronic devices continues to be scaled down to less than 10-nm in size, the line-edge roughness (LER) becomes a critical issue that significantly affects the CD, as well as the device performance because the LER does not scale along with the feature
size. Therefore, the LER needs to be reduced to continue to shrink the feature size as well as minimize the device malfunctions. In this study, the LER impacts on the CD formation with the extreme ultraviolet lithography (EUVL) and the performance of fin-field-effect-transistors (FinFETs)
is investigated using the EUVL model and a compact device method. The LER modeling is conducted using the Monte Carlo method, by describing the stochastic fluctuation of the exposure due to the photon shot noise and resist blur using a three-dimensional (3D) model. The fluctuation of the electric
potentials due to the fin-width roughness (FWR), the electric potentials with fat-fin, thin-fin, big-source, and big-drain FWRs are right shifted, left shifted, down shifted, and upper shifted to the electric potential without FWR, respectively. The fluctuation of the drain currents due to
gate voltages are right shifted in order of the drain currents with fat-fin, big-source, and big-drain FWRs. According to the Taguchi method, the gate voltage and channel length are more dominant for the sensitivity of the electronic potential and current drain of the FinFET device.",
}