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Optimal Geometry Aspect Ratio of Ellipse-Shaped-Surrounding-Gate Nanowire Field Effect Transistors

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Theoretically ideally round shape of the surrounding gate may not always guarantee because of limitations of the fabrication process in surrounding-gate nanowire field effect transistors (FETs). These limitations may lead to the formation of an ellipse-shaped surrounding gate with major and minor axes of different lengths. In this paper, we for the first time study the electrical characteristics of ellipse-shaped-surrounding-gate silicon nanowire FETs with different ratio of the major and minor axes. By simultaneously simulating engineering acceptable magnitudes of the threshold voltage rolloff, the drain induced barrier lowering, the subthreshold swing, and the on-/off-state current ratio, an optimal geometry aspect ratio between the channel length and the major and minor axes of the ellipse-shaped-surrounding-gate nanowire FET is concluded.
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Document Type: Research Article

Publication date: January 1, 2016

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  • Journal for Nanoscience and Nanotechnology (JNN) is an international and multidisciplinary peer-reviewed journal with a wide-ranging coverage, consolidating research activities in all areas of nanoscience and nanotechnology into a single and unique reference source. JNN is the first cross-disciplinary journal to publish original full research articles, rapid communications of important new scientific and technological findings, timely state-of-the-art reviews with author's photo and short biography, and current research news encompassing the fundamental and applied research in all disciplines of science, engineering and medicine.
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