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TCAD Assessment of Dielectrics and Channel Doping Impact in Junctionless Double Gate MOSFET

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In this paper the performance of junctionless double gate MOSFET has been analyzed in the presence of high-k, low-k dielectrics and the impact of channel doping has been observed by using Silvaco TCAD with ATLAS device simulator and compared with the conventional double gate MOSFET. The junction free architecture of junctionless DG MOSFET reduces the short channel effects and manufacturing cost. The high doping concentration of the junctionless DG MOSFET degrades the carrier mobility causing reduction in the drive current and transconductance in comparison to the conventional DG MOSFET. However, the usage of high-K dielectrics shows a remarkable improvement in the transconductance of the device, and interestingly, a sufficient high doping has produced a good drive current in junctionless DG MOSFET.
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Keywords: CHANNEL DOPING; CONVENTIONAL DG MOSFET (DG-MOSFET); DRAIN CURRENT (ID); DRAIN VOLTAGE (VDS); GATE DIELECTRIC; GATE VOLTAGE (VGS); JUNCTIONLESS DG MOSFET (JLDG-MOSFET)

Document Type: Research Article

Publication date: August 1, 2015

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  • Journal of Computational and Theoretical Nanoscience is an international peer-reviewed journal with a wide-ranging coverage, consolidates research activities in all aspects of computational and theoretical nanoscience into a single reference source. This journal offers scientists and engineers peer-reviewed research papers in all aspects of computational and theoretical nanoscience and nanotechnology in chemistry, physics, materials science, engineering and biology to publish original full papers and timely state-of-the-art reviews and short communications encompassing the fundamental and applied research.
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