@article {Khan:2007:1546-1955:1160,
title = "Performance Evaluation of n-Type Carbon Nanotube Field Effect Transistors Using Ca as Contact Electrodes",
journal = "Journal of Computational and Theoretical Nanoscience",
parent_itemid = "infobike://asp/jctn",
publishercode ="asp",
year = "2007",
volume = "4",
number = "6",
publication date ="2007-09-01T00:00:00",
pages = "1160-1165",
itemtype = "ARTICLE",
issn = "1546-1955",
eissn = "1546-1963",
url = "https://www.ingentaconnect.com/content/asp/jctn/2007/00000004/00000006/art00010",
doi = "doi:10.1166/jctn.2007.2393",
keyword = "CARBON NANOTUBE, FIELD EFFECT TRANSISTOR",
author = "Khan, Aurangzeb and Shah, A. Q. S. and Al-Khatib, Mazen and Gou, Jihua",
abstract = "In present technology, carbon nanotube-based field effect transistors (CNTFET) are fabricated with Schottky barriers at the metal/nanotube contact. So far, only p-type CNTFET has been the primary focus of research. However, a digital circuit demands both n-type and p-type devices. In
this research work, a model has been proposed in view of the recent experimental demonstration using Calcium (Ca) as a contact metal to realize the n-type CNTFET. In order to fully optimize the proposed device model, the effects of different parameters such as work function, oxide thickness,
oxide capacitance and source velocity limits were studied. Among all the parameters, the work function of the contact metal plays an important role for controlling the flow of carriers through the carbon nanotube channel and to reduce the threshold voltage. A semi-classical simulation of the
proposed n-type CNTFET has been performed. The results show an excellent sub threshold swing value of 62.91 mV/decade, close to the ITRS specifications. A very good I
on/I
off ratio is achieved that suggests the leakage current for the proposed device is quite
low, making it possible to use this kind of device in VLSI circuits easily. The on-current value of the proposed model is 90% of the ballistic limits, which makes this device a potential candidate to replace current CMOS technology.",
}