Search Results

Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures

Authors: Kissler, Dmitrij; Strawetz, Andreas; Hannig, Frank; Teich, Jürgen

Source: Journal of Low Power Electronics, Volume 5, Number 1, April 2009 , pp. 96-105(10)

Publisher: American Scientific Publishers

Ubiquitous evolvable hardware system for heart disease diagnosis applications

Authors: Kim, Tae Seon; Lee, Hanho; Park, Jaehyun; Lee, Chong-Ho; Lee, Yong-Min; Choi, Chang-Seok; Hwang, Seung-Gon; Kim, Hyun Dong; Min, Chul Hong

Source: International Journal of Electronics, Volume 95, Number 7, July 2008 , pp. 637-651(15)

Publisher: Taylor and Francis Ltd

FPGA-based minutia matching for biometric fingerprint image database retrieval

Authors: Jiang, Richard; Crookes, Danny

Source: Journal of Real-Time Image Processing, Volume 3, Number 3, September 2008 , pp. 177-182(6)

Publisher: Springer

ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing

Authors: Saponara, Sergio; Casula, Michele; Fanucci, Luca

Source: Journal of Real-Time Image Processing, Volume 3, Number 3, September 2008 , pp. 201-216(16)

Publisher: Springer

The Architecture and Development Flow of the S5 Software Configurable Processor

Author: Arnold, Jeffrey

Source: The Journal of VLSI Signal Processing, Volume 47, Number 1, April 2007 , pp. 3-14(12)

Publisher: Springer

A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over F_2¹⁶³ using Gaussian Normal Bases

Authors: Juliato, Marcio; Araujo, Guido; López, Julio; Dahab, Ricardo

Source: The Journal of VLSI Signal Processing, Volume 47, Number 1, April 2007 , pp. 59-76(18)

Publisher: Springer

Exploring opportunities to improve the performance of a reconfigurable instruction set processor

Source: International Journal of Electronics, Volume 94, Number 5, May 2007 , pp. 481-500(20)

Publisher: Taylor and Francis Ltd

A flexible processor for the characteristic 3 &#951;<SUB align=right>T pairing

Authors: Ronan, Robert; Murphy, Colin; Kerins, Tim; O.hEigeartaigh, Colm; Barreto, Paulo S.L.M.

Source: International Journal of High Performance Systems Architecture, Volume 1, Number 2, 14 October 2007 , pp. 79-88(10)

Publisher: Inderscience Publishers

SPA resistant elliptic curve cryptosystem using addition chains

Authors: Byrne, Andrew; Crowe, Francis; Marnane, William Peter; Meloni, Nicolas; Tisserand, Arnaud; Popovici, Emanuel M.

Source: International Journal of High Performance Systems Architecture, Volume 1, Number 2, 14 October 2007 , pp. 133-142(10)

Publisher: Inderscience Publishers

Symmetric encryption in reconfigurable and custom hardware

Authors: Swankoski, Eric J.; Vijaykrishnan, N.; Brooks, R.; Kandemir, M.; Irwin, M.J.

Source: International Journal of Embedded Systems, Volume 1, Numbers 3-4, 5 June 2006 , pp. 205-217(13)

Publisher: Inderscience Publishers

Symmetric encryption in reconfigurable and custom hardware

Authors: Swankoski, Eric J.; Vijaykrishnan, N.; Brooks, R.; Kandemir, M.; Irwin, M.J.

Source: International Journal of Embedded Systems, Volume 1, Numbers 3-4, 5 June 2006 , pp. 205-217(13)

Publisher: Inderscience Publishers

A reconfigurable processor for high speed point multiplication in elliptic curves

Authors: Saqib, Nazar A.; Rodriguez-Henriquez, Francisco; Diaz-Perez, Arturo

Source: International Journal of Embedded Systems, Volume 1, Numbers 3-4, 5 June 2006 , pp. 237-249(13)

Publisher: Inderscience Publishers

A reconfigurable processor for high speed point multiplication in elliptic curves

Authors: Saqib, Nazar A.; Rodriguez-Henriquez, Francisco; Diaz-Perez, Arturo

Source: International Journal of Embedded Systems, Volume 1, Numbers 3-4, 5 June 2006 , pp. 237-249(13)

Publisher: Inderscience Publishers

Parallel algorithms for robot path planning with simpler VLSI architecture

Authors: Arock, Michael; Ponalagusamy, R.

Source: International Journal of Computer Applications in Technology, Volume 26, Number 3, 7 August 2006 , pp. 157-163(7)

Publisher: Inderscience Publishers

Online context switching for real time control applications using reconfigurable fuzzy inference chip

Authors: Cao, Qi; Lim, Meng Hiot; Ling, Keck Voon; Li, Ju Hui; Chan, Ching Wern

Source: International Journal of Computer Applications in Technology, Volume 27, Numbers 2-3, 19 October 2006 , pp. 153-165(13)

Publisher: Inderscience Publishers

A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture

Authors: Mehta, Gayatri; Stander, Justin; Lucas, Josh; Hoare, Raymond R.; Hunsaker, Brady; Jones, Alex K.

Source: Journal of Low Power Electronics, Volume 2, Number 2, August 2006 , pp. 148-164(17)

Publisher: American Scientific Publishers

A RISC architecture extended by an efficient tightly coupled reconfigurable unit

Authors: Vassiliadis, N.; Kavvadias, N.; Theodoridis, G.; Nikolaidis, S.

Source: International Journal of Electronics, Volume 93, Number 6, June 2006 , pp. 421-438(18)

Publisher: Taylor and Francis Ltd

G729 Voice Decoder Design

Authors: Sayadi, Fatma; Casseau, Emmanuel; Atri, Mohamed; Marzougui, Mehrez; Tourki, Rached; Martin, Eric

Source: The Journal of VLSI Signal Processing, Volume 42, Number 2, February 2006 , pp. 173-184(12)

Publisher: Springer

Performance Improvements from Partitioning Applications to FPGA Hardware in Embedded SoCs

Authors: Galanis, Michalis; Dimitroulakos, Gregory; Goutis, Costas

Source: The Journal of Supercomputing, Volume 35, Number 2, February 2006 , pp. 185-199(15)

Publisher: Springer

A dynamic processor management strategy on the reconfigurable meshes

Authors: Seo, Kyung-Hee; Kim, Sung-Chun

Source: International Journal of High Performance Computing and Networking, Volume 3, Number 1, 28 September 2005 , pp. 54-61(8)

Publisher: Inderscience Publishers