Search Results

A Novel Low Energy Scheduling Algorithm for Clustered Very Long Instruction Word Architectures

Authors: Xu, Yang; Hu, He; Yihe, Sun

Source: Journal of Low Power Electronics, Volume 5, Number 2, August 2009 , pp. 123-134(12)

Publisher: American Scientific Publishers

If-conversion for embedded VLIW architectures

Author: Bruel, C.

Source: International Journal of Embedded Systems, Volume 4, Number 1, 18 July 2009 , pp. 2-16(15)

Publisher: Inderscience Publishers

Power-efficient VLIW design using clustering and widening

Authors: Pericas, Miquel; Ayguade, Eduard; Zalamea, Javier; Llosa, Josep; Valero, Mateo

Source: International Journal of Embedded Systems, Volume 3, Number 3, 14 September 2008 , pp. 141-149(9)

Publisher: Inderscience Publishers

Energy-aware compilation and hardware design for VLIW embedded systems

Authors: Ayala, Jose L.; Lopez-Vallejo, Marisa; Atienza, David; Raghavan, Praveen; Catthoor, Francky; Verkest, Diederik

Source: International Journal of Embedded Systems, Volume 3, Numbers 1-2, 2 December 2007 , pp. 73-82(10)

Publisher: Inderscience Publishers

Precomputation-Based Guarding and a Robust Power Gating Strategy in Deep Sub-Micron CMOS

Authors: Abdollahi, Afshin; Pedram, Massoud

Source: Journal of Nanoelectronics and Optoelectronics, Volume 2, Number 2, August 2007 , pp. 171-190(20)

Publisher: American Scientific Publishers

A Low Power, Scalable and Runtime Customizable Microprocessor Architecture for Image Processing

Authors: Notarangelo, Giuseppe; Pappalardo, Francesco; Salurso, Elena; Guidetti, Elio

Source: Journal of Low Power Electronics, Volume 3, Number 1, April 2007 , pp. 36-42(7)

Publisher: American Scientific Publishers

A Scalable Configurable Architecture for Advanced Wireless Communication Algorithms

Authors: Sarrigeorgidis, Konstantinos; Rabaey, Jan

Source: The Journal of VLSI Signal Processing, Volume 45, Number 3, December 2006 , pp. 127-151(25)

Publisher: Springer

Scalable and Structured Scheduling

Author: Feautrier, Paul

Source: International Journal of Parallel Programming, Volume 34, Number 5, October 2006 , pp. 459-487(29)

Publisher: Springer

Reducing Instruction Translation Look-Aside Buffer Energy Through Compiler-Directed Resizing

Authors: Allu, Bramha; Zhang, Wei

Source: Journal of Low Power Electronics, Volume 2, Number 2, August 2006 , pp. 140-147(8)

Publisher: American Scientific Publishers

Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions

Authors: Currie, David; Feng, Xiushan; Fujita, Masahiro; Hu, Alan; Kwan, Mark; Rajan, Sreeranga

Source: International Journal of Parallel Programming, Volume 34, Number 1, March 2006 , pp. 61-91(31)

Publisher: Springer

Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors

Authors: Shao, Zili; Zhuge, Qingfeng; Zhang, Youtao; Sha, Edwin H-M.

Source: International Journal of High Performance Computing and Networking, Volume 1, Numbers 1-2, 5 August 2005 , pp. 4-16(13)

Publisher: Inderscience Publishers

High-performance and low-power VLIW cores for numerical computations

Authors: Pericas, Miquel; Ayguade, Eduard; Zalamea, Javier; Llosa, Josep; Valero, Mateo

Source: International Journal of High Performance Computing and Networking, Volume 1, Number 4, 7 December 2005 , pp. 171-179(9)

Publisher: Inderscience Publishers

Register Saturation in Instruction Level Parallelism

Author: Touati, Sid-Ahmed-Ali

Source: International Journal of Parallel Programming, Volume 33, Number 4, August 2005 , pp. 393-449(57)

Publisher: Springer

A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications

Authors: Stolberg, Hans-Joachim; Berekovi, Mladen; Pirsch, Peter

Source: The Journal of VLSI Signal Processing, Volume 41, Number 2, September 2005 , pp. 139-151(13)

Publisher: Springer

A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures

Authors: Barbieri, Ivano; Bariani, Massimo; Cabitto, Alberto; Raggio, Marco

Source: The Journal of VLSI Signal Processing, Volume 41, Number 2, September 2005 , pp. 153-168(16)

Publisher: Springer

IEEE-Compliant IDCT on FPGA-Augmented TriMedia

Authors: Sima Mihai; Cotofaná Sorin; Eijndhoven Jos; Vassiliadis Stamatis; Vissers Kees

Source: The Journal of VLSI Signal Processing, Volume 39, Number 3, March 2005 , pp. 195-212(18)

Publisher: Springer

PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing

Authors: Lee Ruby; Fiskiran A.

Source: The Journal of VLSI Signal Processing, Volume 40, Number 1, May 2005 , pp. 85-108(24)

Publisher: Springer

Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures

Authors: Javier Zalamea; Josep Llosa; Eduard Ayguadé; Mateo Valero

Source: International Journal of Parallel Programming, Volume 32, Number 6, December 2004 , pp. 447-474(28)

Publisher: Springer

Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors

Authors: Masselos K.; Catthoor F.; Goutis C.E.; DeMan H.

Source: The Journal of VLSI Signal Processing, Volume 37, Number 1, May 2004 , pp. 53-73(21)

Publisher: Springer

SPOT-Development tool for software pipeline optimization for VLIW-DSPs used in real-time image processing

Authors: Furtler J.; Mayer K.J.; Krattenthaler W.; Bajla I.

Source: Real-Time Imaging, Volume 9, Number 6, December 2003 , pp. 387-399(13)

Publisher: Elsevier