Search Results

Selective Forward Body Bias for High Speed and Low Power SRAMs

Authors: Bollapalli, Kalyana C.; Garg, Rajesh; Gulati, Kanupriya; Khatri, Sunil P.

Source: Journal of Low Power Electronics, Volume 5, Number 2, August 2009 , pp. 185-195(11)

Publisher: American Scientific Publishers

Design of Low Power Adiabatic SRAM Using DTGAL, CPAL and ACPL: A Comparative Study

Authors: Sudharshan, Y.K.; Sreenu, D.; Saxena, A.K.; Dasgupta, S.

Source: Journal of Low Power Electronics, Volume 5, Number 1, April 2009 , pp. 40-49(10)

Publisher: American Scientific Publishers

A proposed SRAM cell for low power consumption during write operation

Authors: Prabhu, C.M.R.; Singh, Ajay Kumar

Source: Microelectronics International, Volume 26, Number 1, 2009 , pp. 37-42(6)

Publisher: Emerald Group Publishing Limited

Bosque: integrated phylogenetic analysis software

Authors: Ramírez-Flandes, Salvador; Ulloa, Osvaldo

Source: Bioinformatics, Volume 24, Number 21, 1 November 2008 , pp. 2539-2541(3)

Publisher: Oxford University Press

MODELING OF A FERROELECTRIC FIELD-EFFECT TRANSISTOR STATIC RANDOM ACCESS MEMORY CELL

Authors: Phillips, Thomas; Macleod, Todd; Ho, Fat

Source: Integrated Ferroelectrics, Volume 96, Number 1, 2008 , pp. 69-74(6)

Publisher: Taylor and Francis Ltd

Design of a Low Leakage, Low Power and High Performance Search and Read Memory Using CAM and SRAM

Authors: Dandapat, A.; Kayal, D.; Mukhopadhyay, D.

Source: Journal of Low Power Electronics, Volume 4, Number 2, August 2008 , pp. 158-168(11)

Publisher: American Scientific Publishers

Application-Driven Simulation of Nanoscaled CMOS Transistors and Circuits

Authors: Burenkov, A.; Kampen, C.; Baer, E.; Lorenz, J.; Ryssel, H.

Source: Journal of Computational and Theoretical Nanoscience, Volume 5, Number 6, June 2008 , pp. 1170-1182(13)

Publisher: American Scientific Publishers

An Exploratory Design Study of a 16 × 16 Static Random Access Memory Using Silicon Nanowire Transistors

Authors: Bindal, Ahmet; Hamedi-Hagh, Sotoudeh

Source: Journal of Nanoelectronics and Optoelectronics, Volume 2, Number 3, December 2007 , pp. 294-303(10)

Publisher: American Scientific Publishers

Design of power-aware FPGA fabrics

Authors: Gayasen, Aman; Srinivasan, Suresh; Vijaykrishnan, N.; Kandemir, Mahmut

Source: International Journal of Embedded Systems, Volume 3, Numbers 1-2, 2 December 2007 , pp. 52-64(13)

Publisher: Inderscience Publishers

Hardware event-driven simulation engine for spiking neural networks

Source: International Journal of Electronics, Volume 94, Number 5, May 2007 , pp. 469-480(12)

Publisher: Taylor and Francis Ltd

Enhanced multi-level filter algorithm and its VLSI architecture

Source: International Journal of Electronics, Volume 94, Number 2, February 2007 , pp. 157-169(13)

Publisher: Taylor and Francis Ltd

Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs

Authors: Sterpone, L.; Sonza Reorda, M.; Violante, M.; Kastensmidt, F.; Carro, L.

Source: Journal of Electronic Testing, Volume 23, Number 1, February 2007 , pp. 47-54(8)

Publisher: Springer

Design perspective against random dopant fluctuation and process variation for scaling multi-gate devices

Authors: Ashizawa, Yoshio; Tanabe, Ryo; Oka, Hideki

Source: Journal of Computational Electronics, Volume 5, Number 4, December 2006 , pp. 319-322(4)

Publisher: Springer

Dynamically configurable security for SRAM FPGA bitstreams

Authors: Bossuet, Lilian; Gogniat, Guy; Burleson, Wayne

Source: International Journal of Embedded Systems, Volume 2, Numbers 1-2, 5 July 2006 , pp. 73-85(13)

Publisher: Inderscience Publishers

Dynamically configurable security for SRAM FPGA bitstreams

Authors: Bossuet, Lilian; Gogniat, Guy; Burleson, Wayne

Source: International Journal of Embedded Systems, Volume 2, Numbers 1-2, 5 July 2006 , pp. 73-85(13)

Publisher: Inderscience Publishers

WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays

Authors: Gomathisankaran, Mahadevan; Tyagi, Akhilesh

Source: Journal of Low Power Electronics, Volume 2, Number 3, December 2006 , pp. 388-400(13)

Publisher: American Scientific Publishers

SRAM Cell Optimization for Ultra-Low Power Standby

Authors: Qin, Huifang; Vattikonda, Rakesh; Trinh, Thuan; Cao, Yu; Rabaey, Jan

Source: Journal of Low Power Electronics, Volume 2, Number 3, December 2006 , pp. 401-411(11)

Publisher: American Scientific Publishers

Static Random Access Memory Cells with Intrinsically High Read Stability and Low Standby Power

Authors: Badrudduza, Sayeed A.; Samson, Giby; Clark, Lawrence T.

Source: Journal of Low Power Electronics, Volume 2, Number 3, December 2006 , pp. 412-424(13)

Publisher: American Scientific Publishers

Reducing Power Dissipation in SRAM during Test

Authors: Dilillo, Luigi; Rosinger, Paul; Al-Hashimi, Bashir M.; Girard, Patrick

Source: Journal of Low Power Electronics, Volume 2, Number 2, August 2006 , pp. 271-280(10)

Publisher: American Scientific Publishers

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

Authors: Girard, Patrick; Héron, Olivier; Pravossoudovitch, Serge; Renovell, Michel

Source: Journal of Electronic Testing, Volume 22, Number 2, April 2006 , pp. 161-172(12)

Publisher: Springer