Search Results

Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level

Authors: Viswanath, Vinod; Vasudevan, Shobha; Abraham, Jacob A.

Source: Journal of Low Power Electronics, Volume 5, Number 3, October 2009 , pp. 339-353(15)

Publisher: American Scientific Publishers

Design and Implementation of a Fast Digital Fuzzy Logic Controller Using FPGA Technology

Authors: Deliparaschos, K.; Nenedakis, F.; Tzafestas, S.

Source: Journal of Intelligent and Robotic Systems, Volume 45, Number 1, January 2006 , pp. 77-96(20)

Publisher: Springer

Algorithm/Architecture Co-exploration for Designing Energy Efficient Wireless Channel Estimator

Authors: Meng, Yan; Gong, Wenrui; Kastner, Ryan; Sherwood, Timothy

Source: Journal of Low Power Electronics, Volume 1, Number 3, December 2005 , pp. 238-248(11)

Publisher: American Scientific Publishers

Flexible Implementation of a WCDMA Rake Receiver: Special Issue on Signal Processing for Broadband Communications (Guest Editors: Naresh R. Shanbhag and Keshab K. Parhi)

Authors: Lasse Harju; Mika Kuulusa; Jari Nurmi

Source: The Journal of VLSI Signal Processing, Volume 39, Numbers 1-2, January 2005 , pp. 147-160(14)

Publisher: Springer

Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation

Authors: Navabi, Zainalabedin; Mirkhani, Shahrzad; Lavasani, Meisam; Lombardi, Fabrizio

Source: Journal of Electronic Testing, Volume 20, Number 6, December 2004 , pp. 575-589(15)

Publisher: Springer

Automatic implementation of affine iterative algorithms: Design flow and communication synthesis

Authors: Marongiu A.; Palazzari P.

Source: Computer Physics Communications, Volume 139, Number 1, 1 September 2001 , pp. 109-131(23)

Publisher: Elsevier

The Formal Design of 1M-gate ASICs

Author: Eiríksson Á.þ.

Source: Formal Methods in System Design, Volume 16, Number 1, January 2000 , pp. 7-22(16)

Publisher: Springer

High-Level Controllability and Observability Analysis for Test Synthesis

Authors: Hsu F.F.; Patel J.H.

Source: Journal of Electronic Testing, Volume 13, Number 2, October 1998 , pp. 93-103(11)

Publisher: Springer

Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits

Authors: Ravi S.; Ghosh I.; Roy R.K.; Dey S.

Source: Journal of Electronic Testing, Volume 13, Number 2, October 1998 , pp. 201-212(12)

Publisher: Springer

Redundancy Removal during High-Level Synthesis Using Scheduling Don't-Cares

Author: Wolf W.

Source: Journal of Electronic Testing, Volume 11, Number 3, December 1997 , pp. 211-225(15)

Publisher: Springer

Synthesis of systems specified as interacting VHDL processes

Authors: Eles P.; Kuchcinski K.; Zebo P.

Source: Integration, the VLSI Journal, Volume 21, Number 1, November 1996 , pp. 113-138(26)

Publisher: Elsevier